Reducing power consumption is of paramount importance in semiconductor integrated circuits employed in mobile telephones and the like. A method of controlling substrate bias is one method of reducing power consumption in semiconductor integrated circuit devices. Substrate bias refers to the application of voltage to a well formed in the substrate of a transistor (namely to the back gate of the transistor). By way of example, when a transistor is operating, a forward substrate bias (which diminishes the potential difference between the gate and back gate) is applied, thereby facilitating the flow of current in the channel of the transistor and speeding up operation. When a transistor is non-operational, on the other hand, a reverse substrate bias (which enlarges the potential difference between the gate and back gate) is applied, thereby diminishing leakage of current and reducing power consumption. Such substrate bias is supplied via substrate-bias control wiring that is laid separate from ordinary power-supply wiring. Further, the wiring for substrate-bias control can take on a potential higher than the power-supply voltage or lower than ground voltage particularly when reverse substrate bias is applied.
An increase in device functionality and versatility has been accompanied by an increase in the degree of integration of semiconductor integrated circuit devices and in the density of wiring in such devices. In already existing routing processes, routing is performed so as to maintain a prescribed minimum spacing. More specifically, in a case where substrate-bias control is not performed, a design method implemented by a design system is carried out to perform routing in such a manner that the minimum necessary wiring spacing will be adopted as the prescribed minimum spacing in order to assure reliability even if the maximum potential difference develops between the power supply and ground. On the other hand, a design method of assuring insulation between wiring traces by causing an automatic routing tool to recognize the potential of each wiring trace and changing the wiring spacing in accordance with the potential difference between traces has been disclosed in Patent Document 1. This method includes inputting net-list data that specifies the potentials of wiring networks and creating wiring layout data based upon wiring spacing that corresponds to the potential difference between networks.
[Patent Document 1] Japanese Patent Kokai Publication No. JP-P2003-31664A